The present invention relates to an improved semiconductor memory and a method of using the same, to an improved column decoder, and to an improved image processor. More particularly, it relates to a semiconductor memory having an effective application to an image memory for use in image processing and a method of using the same, to a column decoder which eliminates the need for complicated address calculation outside the memory when image data is mapped at an appropriate position to be stored, and to an image processor comprising the above semiconductor memory and a parallel arithmetic processor and having an effective application to image processing.
An image memory is for storing image data to be used in an image processing apparatus having an image displaying function and is one of the important applications of a semiconductor memory. As the image memory, there is used a dual port memory (VRAM) comprising: a random-access memory (RAM) for storing image data; and a serial-access memory (SAM) for storing data corresponding to one line of the RAM. The VRAM enables an access to the RAM through a random port: and an access to the SAM through a serial port.
In the VRAM, an access to the RAM for displaying image data is made through the serial port of the SAM using one line of data as a unit, thereby reducing the number of accesses to the RAM for displaying image data and extending the period during which an access to the RAM for image processing can be made through the random port. Therefore, the VRAM is useful for high-speed image processing.
FIG. 20 shows an example of the structure of a memory core portion of a conventional VRAM.
In the drawing, a RAM 9 is constituted by: a memory cell array composed of a large number of memory cells MC disposed at individual intersections of word lines W0 to Wn and bit lines BL0, /BL0 to BLm, and /BLm; a column decoder 1; a column select gate 2; and a sense amplifier 3, while a SAM 10 is constituted by: a data transfer gate 7 connected to the bit lines BL0, /BL0 to BLm, and /BLm; a serial register 4; a counter 6; and a SAM decoder 5.
In an access to the RAM 9 through a random port, the memory cell array is accessed via a random data I/O line. Specifically, one of the word lines is selected based on a row address and data in the memory cells connected to the selected word line is amplified by the sense amplifier 3 and then outputted onto the bit lines BL0, /BL0 to BLm, and /BLm. Thereafter, a signal from the column decoder 1 for decoding a column address drives a column select gate 2, which selectively connects a given one of the above bit lines BL0, /BL0 to BLm, and /BLm to the random data I/O line, thereby reading or writing data from or in the memory cell selected based on the row address and column address. In this manner, a random access is made to the RAM 9 through the random data I/O line.
On the other hand, in reading one line of data from the RAM 9 through the serial port of the SAM 10, one of the word lines is selected based on a row address and one line of data in the plurality of memory cells connected to -the selected word line is amplified by the sense amplifier 3 and then outputted onto the bit lines BL0, /BL0 to BLm, and /BLm. By controlling a data transfer signal 8, the plural sets of data outputted onto the above bit lines BL0, /BL0 to BLm, and /BLm are transferred to the serial register 4 via the transfer gate 7. The counter 6 for counting a serial clock is caused to generate a serial address, while the SAM decoder 5 for decoding the serial address outputs a select signal, which designates a selected bit position. Accordingly, by counting up the serial clock by means of the counter 6, the plural sets of data in the serial register 4 are sequentially selected, thereby successively reading the serial data onto an output line.
FIG. 21 shows an example of the structure of an image processing system using the VRAM of FIG. 20. A VRAM 100 comprising the RAM 9 and the SRAM 10 is connected through a random port 106 to a system bus 104. Image processing by a CPU 103 is executed by making an access to the RAM 9 via the system bus 104 through the random port 106.
In the case of displaying data in the RAM 9, one line of data in the RAM 9 is transferred to the SAM 10, serially read through the serial port 107, and then given to a display unit 105, thereby displaying the data.
In this manner, the conventional VRAM can transfer one line of data in the RAM to the SRAM. Consequently, in the case of outputting data to be displayed to the display unit with the image processing system using the VRAM, the outputting of data is accomplished by transferring one line of data in the RAM to the SRAM and then serially reading the transferred data. As a result, an access to the RAM for displaying data is performed via the SRAM using one line of data as a unit, so that the number of accesses to the RAM for displaying data can be reduced.
However, in order to constitute the VRAM such that image data is stored in the RAM and that one line of data is transferred to the SRAM as the data to be displayed, a one-to-one correspondence should be provided between the address of the stored image data on a display screen and the address thereof in the RAM. In other words, data in a line (column) direction on the display screen should be stored in the memory cells aligned along one of the word lines in the RAM. Consequently, in the case of making an access to data in a rectangular region of the image data in two-dimensional layout (hereinafter referred to as a set of rectangular-region data), the access cannot be made in a page mode cycle of the memory, i.e., in a mode in which a high-speed access is made with respect to the plurality of memory cells on the same word line by varying only the column address, so that it becomes necessary to switch to another word line several times. Therefore, it is difficult to perform high-speed image display.
The conventional VRAM is also disadvantageous in that it cannot excel a general-purpose DRAM in the speed at which an access is made to the RAM through the random port, since the conventional VRAM is aimed at extending the period during which an access to the RAM for image processing can be made through the random port by reducing the number of accesses to the RAM for displaying data and hence is equal to the general-purpose DRAM in the function of making an access to the RAM storing image data through the random port.
To be more specific about the speed at which an access is made to the above RAM through the random port, since a graphics system and an image processing system, e.g., are for processing image data laid out in two dimensions, if a high-speed access can be made to a set of rectangular-region data of the image data laid out in two dimensions, processing performance can be enhanced. Although the enhancement of graphics-drawing ability has been required in the graphics system and an increase in the processing speed at which an image is compressed/expanded has been required in the image processing system, if a correspondence is provided between a plurality of memory cells aligned along a word line in a RAM and a set of rectangular-region image data such that an access can be made to the rectangular-region data in the page mode cycle of the memory, high-speed operation can be intended. However, since the one-to-one correspondence should be provided between the address on the screen and the address in the RAM in the conventional VRAM as described above, data in a line direction of the image data has been stored in the memory cells aligned along one of the word lines in the RAM. Consequently, the above requirement that a correspondence should be provided between a plurality of memory cells aligned along one of the word lines in the RAM and a set of rectangular-region image data cannot be satisfied, so that the speed at which an access is made through the random port cannot be increased.
On the other hand, in the case where a general-purpose DRAM, instead of the above-mentioned VRAM, adopts the structure in which a correspondence is provided between a plurality of memory cells along a word line of a RAM and a set of rectangular-region data of image data so that an access can be made to the rectangular-region data in the page mode cycle of the memory, one line of data in the RAM cannot be transferred to a SAM at one time if it becomes necessary to display the image data on the display screen, but only one line of data at a time. Consequently, switching to another word line is required several times in order to display one line of data on the display screen, which makes it difficult to perform high-speed image display.